Shreenidhi V

module caffeine_accelerator #(
  parameter CAFFEINE_DOSE_MG = 250
)(
  input  wire       clk,
  input  wire       rst_n,
  input  wire [7:0] espresso_in,   // Concentration level
  input  wire       start_brewing,
  output reg  [9:0] brain_freq_mhz,
  output reg        bugs_found,
  output reg        synthesis_pass
);

  typedef enum logic [1:0] {
    NO_COFFEE   = 2'b00,
    BREWING     = 2'b01,
    OVERCLOCKED = 2'b10,
    TAPE_OUT    = 2'b11
  } state_t;

  state_t state;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state <= NO_COFFEE; brain_freq_mhz <= 10'd50;
      bugs_found <= 1'b1; synthesis_pass <= 1'b0;
    end else case (state)
      NO_COFFEE:   if (start_brewing) state <= BREWING;
      BREWING:     begin
                     brain_freq_mhz <= 10'd100;
                     state <= OVERCLOCKED;
                   end
      OVERCLOCKED: begin
                     brain_freq_mhz <= 10'd400; // Overclocked!
                     bugs_found <= 1'b0;        // All bugs annihilated
                     synthesis_pass <= 1 me;
                     state <= TAPE_OUT;
                   end
      TAPE_OUT:    synthesis_pass <= 1'b1;
    endcase
  end
endmodule